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MSR dramatically simplifies the turning table mechanical transmission system. In many cases, it is also much more economical.
Up to now, the most conventional solution for turntable drives has been composed of: a main drive (single pinion) for turning operation and a feed-preload gearbox (Dual pinions) for C axis drive milling operations. This complex and rather expensive gearbox allows additional operations such as milling.
In this configuration, a main drive provides the total driving torque, which is transmitted continuously to the table which holds the spindle. It is generally composed of a spur-gearbox including a 2-speed gearbox to extend the constant power range according to work piece diameters min/max. It delivers high torque at low speeds to slug out steel or cast iron and permits high speeds for trim or finish cuts.
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C-axis drive provides total driving torque 100% at low speed for milling operations. The two pinions need to be disconnected during turning operation and the main drive need to be shifted onto neutral ratio.
REDEX ANDANTEX is introducing a new solution to the market. It benefits from new drive and control systems (for example Siemens CNC or Fanuc).
Main drive is composed of two identical gearboxes (Twin pinions) sharing the driving torque (50%-50%) during turning operations. The CNC system manages a motor preload torque to cancel backlash. One motor is driving and the other motor is braking during milling operations.
Because, it enables very accurate positioning, it allows for the execution of additional duties on the C axis, without any additional mechanical device.
For this new drive solution, REDEX ANDANTEX has developed a turnkey solution made with MSD 2-speed gearbox combined with the R SERIE bevel box. This integrated and compact system is ready to be implemented. Depending on machine arrangement, OEM can use bevel box as an option.
This new range consist of 4 sizes, MSD35R31- MSD35R41- MSD60R41- MSD60R51 with torque capacity at pinion from 2000/4000Nm (2 x 40Kw motors) up to 9000/18000Nm (2 x 100Kw motors) with two possible ratios of 7.66&2 and 9.88&2.
This solution, combined with pinion/ring ratio of about 10 to 15 offers: 1) Turn table torques from 20 0000Nm up to 270 000Nm. 2) Global ratios (gearbox + ring gear) of 77/20 and 148/30.
For new turning table developments, this solution is much simpler and economical. In particular, it eliminates the need for developing a complex and expensive gearbox for the C axis.
For existing systems, it also offers numerous advantages. A solution with two motors is much less expensive and easier to manage. In the case of a high duty turning table in the conventional configuration a 160kW motor, the MSR would use two 80kW motors, which are more standard and less expensive, despite the fact that there are two of them. Spare parts management is also much easier to manage with a smaller motor. Further, there is no need to manage the C-axis gearbox manufacturing with all its components.
REDEX ANDANTEX, headquartered in Ferrières, France, employs 320 persons and has three production sites in Europe and North America. More than 75% of sales are generated outside France. Technological progress, a commitment to quality and exceptional technical support are the fundamental values of REDEX ANDANTEX.
For further information, e-mail: cfourtune@redex.fr Refer to page 162
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The eSi-RISC Development Suite v2.1, from EnSilca, provides a comprehensive platform for easily evaluating EnSilica's family of eSi-RISC highly configurable and low-power soft processor cores, along with a complete development environment for the creation, implementation and test of eSi-RISC processor embedded application designs.
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The eSi-RISC Development Suite v2.1 includes a hardware evaluation platform based on Altera's Cyclone III FPGA with rapid software development and debugging facilitated through the Eclipse IDE (Integrated Development Environment) and industry-standard GNU GCC 4.4.0 toolchain, which now features native support for the eSi-RISC architectural features. FPGA configurations are supplied for the complete eSi-RISC processor family, along with numerous application examples demonstrating how the system-on-chip peripherals can be used, including a full port of the open source FreeRTOS with lwIP TCP/IP network stack. Comprehensive documentation and a range of interactive tutorials are also included.
Extensive debug facilities in the eSi-RISC Development Suite v2.1 also significantly enhance development productivity. Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints and control program execution, giving developers full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly. Debugging is seamless with communication over a USB interface to a host PC with GDB, the GNU project debugger, running inside Eclipse.
The eSi-RISC Development Suite v2.1 also allows developers to debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics' ModelSim from the Eclipse GDB project debugger through a network socket connection. ModelSim conveniently displays disassembled instructions as text in the wave display which is especially helpful for SoC level hardware and software debugging.
Network application debugging is also considerably simplified with the integration of WinPcap into the new eSi-RISC Development Suite's Instruction Set Simulator to emulate the eSi-EMAC Ethernet MAC peripheral connection. This makes it possible, for instance, to run a Web Server on eSi-RISC with a live Ethernet connection serving web pages to a browser running on a remote computer.
"The ease and speed with which processors can be evaluated and applications developed and tested, plays an important role in developers' choice of processors," said Ian Lankshear, Managing Director of EnSilica. "The eSi-RISC Development Suite v2.1 includes a host of features and capabilities to enable our eSi-RISC processor family to be easily evaluated and quickly deployed."
The eSi-RISC processor family
eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scales across a wide range of applications and uniquely supports both 16 and 32-bit configurations. The eSi-RISC family of processors has been extensively silicon proven in a number of ASIC and FPGA technologies.
The eSi-RISC family includes the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSI-3250 32 bit processor and eSi-3250sfp incorporating a single precision floating point processor. The processor cores also benefit from selectable Harvard/von Neumann memory and configurable cache options. The highly pipelined nature of their design gives customers a technology-independent solution that is ideal for both FPGA applications and ASIC technologies.
Ensilica in profile
EnSilica is an established company with many years experience providing high quality IC design services to customers undertaking FPGA and ASIC designs. EnSilica has an impressive record of success working across many market segments with particular expertise in multimedia and communications applications. Customers range from start-ups to blue-chip companies. EnSilica can provide the full range of front-end IC design services, from System Level Design, RTL coding and Verification through to either a FPGA device or the physical design interface (synthesis, STA, DFT) for ASIC designs. EnSilica also offers a portfolio of IP, including a highly configurable 16/32 bit embedded processor called eSi-RISC and the eSi-Comms range of communications IP.
For further information about EnSilica, view website: http://www.ensilica.com and eSi-RISC product information can be downloaded at: http://www.esi-risc.com
Further information can also be obtained via e-mail: david.wheeler@ensilica.com Refer to page 68
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